The present invention relates to integrated circuit chips and, in particular, to a method and apparatus for conveniently testing the design of such chips prior to their fabrication.
Electronic systems of all types, including computer systems, are largely constructed from integrated circuit chips. The design of such systems is quite different from systems that employ only discrete circuit components.
For example, the designer of such systems must normally make an initial choice of whether the integrated circuit chips selected for use in the system either should be "off-the-shelf" or standard chips that are readily available or should be custom chips that are designed for that particular system. Standard chips usually have the advantage of low cost. In addition, since they are readily available, they can be incorporated into the system early in its development, so that the system can be tested even though it is only partially constructed. However, standard chips normally have the disadvantage of not being able to perform uncommon or complex circuit functions. If a complex circuit function is needed, usually several such standard chips must be interconnected to each other.
Custom or customized integrated circuit chips, on the other hand, can be designed so that a complex or uncommon circuit function can be performed by a single chip. However, custom chips have the disadvantages of being more expensive than standard chips and of normally requiring a great deal of manufacturing time after the final design of the system is decided upon.
In the design of a large computer system, the amount of time that it takes to manufacture a custom integrated circuit chip after a final system design can lead to difficulties in testing the operation of the entire system. For example, while individual circuit designs can often be simulated and tested using conventional software techniques, such as by use of the well-known TEGAS programming language, the known techniques do not permit the entire system to be accurately simulated so that problems encountered only when two or more of the chips are interconnected are made evident and can be isolated for correction. Accordingly, it is not until the actual chips have been manufactured, sometimes as much as six months or more after the design is finalized, that the system can be tested for problems of this type.
Often it is only after all the chips are available that such problems can be detected. For example, an integrated circuit chip may have digital logic circuitry that is logically accurate but that gives rise to slight clocking or synchronizing errors that cause data to be generated slightly ahead or behind its expected occurrence. This will often significantly affect some other chip whose operation is dependent upon such data. If such an error is not detected until the chips have been manufactured, which may be several months after all chip designs have been finalized, it is necessary for the chip giving rise to the error to be redesigned and again manufactured. Of course, the final assembly of the entire system is delayed until the redesigned chip is manufactured.
There has therefore arisen the need, in a method for manufacturing integrated circuit chips, for a method and apparatus for simulating and testing each of the chips that are designed for a large system, so that difficulties which will occur as a result of interconnecting the chips will become evident prior to their manufacture.